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ds20005610a-page 1 ? 2016 microchip technology inc. mic4607 features ? gate drive supply voltage up to 16v ? overcurrent protection ? drives high-side and low-side n-channel mosfets with independent inputs or with a single pwm signal ? ttl input thresholds ? on-chip bootstrap diodes ? fast 35 ns propagation times ? shoot-through protection ? drives 1000 pf load with 20 ns rise and fall times ? low power consumption ? supply undervoltage protection ? ?40c to +125c junction temperature range applications ? three-phase and bldc motor drives ? three-phase inverters general description the mic4607 is an 85v, three-phase mosfet driver. the mic4607 features a fast (35 ns) propagation delay time and a 20 ns driver rise/fall time for a 1 nf capacitive load. ttl inputs can be separate high- and low-side signals or a single pwm input with high and low drive generated internally. high- and low-side outputs are guaranteed to not overlap in either mode. the mic4607 includes overcurrent protection as well as a high-voltage internal diode that charges the high-side gate drive bootstrap capacitor. a robust, high-speed, and low-power level shifter provides clean level transitions to the high-side output. the robust operation of the mic4607 ensures that the outputs are not affected by supply glitches, hs ringing below ground, or hs slewing with high-speed voltage transitions. undervoltage protection is provided on both the low-side and high-side drivers. the mic4607 is available in a both a 28-pin 4 mm 5 mm qfn and 28-pin tssop package with an operating junction temperature range of ?40c to +125c. typical application circuit mic4607 three-phase motor driver 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent protection
mic4607 ds20005610a-page 2 ? 2016 microchip technology inc. package type mic4607-1 28-pin qfn mic4607-1 28-pin tssop mic4607-2 28-pin qfn mic4607-2 28-pin tssop
? 2016 microchip technology inc. ds20005610a-page 3 mic4607 functional diagram mic4607 xphase top-level functional diagram mic4607 xphase top-level functional diagram input logic block
mic4607 ds20005610a-page 4 ? 2016 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ?, ( note 2 ) supply voltage (v dd , v xhb ? v xhs ).............................................................................................................................. ....... ?0.3v to 18v input voltages (v xli , v xhi , v xpwm , v en )................................................................................................................... ?0.3v to v dd + 0.3v flt/ pin....................................................................................................................... ............................................. ?0.3v to v dd + 0.3v dly pin ........................................................................................................................ ....................................................... ?0.3v to 18v voltage on xlo (v xlo ).............................................................................................................................. ................ ?0.3v to v dd + 0.3v voltage on xho (v xho ) .............................................................................................................................. ......v hs ? 0.3v to v hb + 0.3v voltage on xhs (continuous).................................................................................................... ............................................. ?1v to 90v voltage on xhb ................................................................................................................. ............................................................... 108v ilim+ .......................................................................................................................... ......................................................... ?0.3v to +5v ilim? .......................................................................................................................... ......................................................... ?0.3v to +2v average current in v dd to hb diode ................................................................................................................... ........................ 100 ma esd protection on all pins ( note 1 ): hbm ............................................................................................................................ ...................................................... 1 kv mm ............................................................................................................................. ...................................................... 200v cdm............................................................................................................................ ..................................................... 200v operational characteristics ??, ( note 2 ) supply voltage (v dd ), [decreasing v dd ] ............................................................................................................................. 5 .25v to 16v supply voltage (v dd ), [increasing v dd ] .............................................................................................................................. .. 5.5v to 16v voltage on xhs ................................................................................................................. ..................................................... ?1v to 85v voltage on xhs (repetitive transient <100 ns).................................................................................. ...................................... ?5v to 90v hs slew rate................................................................................................................... ............................................................ 50 v/ns voltage on xhb ................................................................................................................. ............................... v hs + 5.5v to v hs + 16v and/or ......................................................................................................................... ................................... v dd ?1v to v dd +85v ? notice: exceeding the absolute maximum ratings may damage the device. ?? notice: the device is not guaranteed to function outside its operating ratings. note 1: devices are esd sensitive. handling precautions are recommended. human body model, 1.5 k in series with 100 pf. 2: an ?x? in front of a pin name refers to either a, b or c phase. (e.g. xhi can be either ahi, bhi or chi).
? 2016 microchip technology inc. ds20005610a-page 5 mic4607 dc characteristics ( note 1 , 2 ) electrical characteristics: unless otherwise indicated, v dd = v xhb = 12v; v en = 5v; v ss = v hs = 0v; no load on xlo or xho; t a = 25c; unless noted. bold values indicate ?40c< t j < +125c. parameters sym. min. typ. max. units conditions supply current v dd quiescent current i dd ? 390 750 a xli = xhi = 0v v dd shutdown current i ddsh ? 2.2 10 a xli = xhi = 0v; en = 0v with hs = floating ? 58 150 xli = xhi = 0v ; en = 0v; hs = 0v v dd operating current i ddo ? 0.6 1.5 ma f = 20 khz per channel xhb quiescent current i hb ? 20 75 a xli = xhi = 0v or xli = 0v and xhi = 5v per channel xhb operating current i hbo ? 30 400 a f = 20 khz xhb to v ss current, quiescent i hbs ? 0.05 5 av xhs = v xhb = 90v xhb to v ss current, operating i hbso ? 30 300 a f = 20 khz input (ttl: xli, xhi, xpwm, en) ( note 3 ) low-level input voltage v il ?? 0.8 v ? high-level input voltage v ih 2.2 ?? v ? input voltage hysteresis v hys 0.1 ? v ? input pull-down resistance r i 100 300 500 k xli and xhi inputs (-1 version) 50 130 250 xpwm input (-2 version) undervoltage protection v dd falling threshold v ddr 3.8 4.4 4.9 v ? v dd threshold hysteresis v ddh ? 0.25 ? v ? xhb falling threshold v hbr 4.0 4.4 4.9 v ? xhb threshold hysteresis v hbh ? 0.25 ? v ? overcurrent protection rising overcurrent threshold v ilim+ 175 200 225 mv (v ilim+ ? v ilim? ) ilim to gate propagation delay t ilim_prop ? 70 ? ns v ilim+ = 0.5v peak fault circuit flt/ output low voltage v olf ? 0.2 0.5 v v ilim = 1v; i flt/ = 1 ma rising dly threshold v dly+ ? 1.5 ? v ? dly current source i dly 0.3 0.44 0.6 av dly = 0v fault clear time t fcl ? 670 ? sc dly = 1 nf bootstrap diode low-current forward voltage v dl ? 0.4 0.70 vi vdd-xhb = 100 a high-current forward voltage v dh ? 0.8 1 vi vdd-xhb = 50 ma note 1: ?x? in front of a pin name refers to either a, b or c phase. (e.g. xhi can be either ahi, bhi or chi). 2: specification for packaged product only. 3: v il(max) = maximum positive voltage applied to the input which will be accepted by the device as a logic low. v ih(min) = minimum positive voltage applied to the input which will be accepted by the device as a logic high. 4: guaranteed by design. not production tested.
mic4607 ds20005610a-page 6 ? 2016 microchip technology inc. dynamic resistance r d ?4 6 v? xlo gate driver low-level output voltage v oll ? 0.3 0.6 v i xlo = 50 ma high-level output voltage v ohl ? 0.5 1 v i xlo = ? 50 ma, v ohl = v dd ? v xlo peak sink current i ohl ?1 ?av xlo = 0v peak source current i oll ?1 ?av xlo = 12v xho gate driver low-level output voltage v olh ? 0.3 0.6 v i xho = 50 ma high-level output voltage v ohh ? 0.5 1 v i xho = ? 50 ma, v ohh = v xhb ? v xho peak sink current i ohh ?1 ?av xho = 0v peak source current i olh ?1 ?av xho = 12v switching specifications (li/hi mode with inputs non-overlapping, assumes hs low before li goes high and lo low before hi goes high). lower turn-off propagation delay (li falling to lo falling) t lphl ? 35 75 ns ? upper turn-off propagation delay (hi falling to ho falling) t hphl ? 35 75 ns ? lower turn-on propagation delay (li rising to lo rising) t lplh ? 35 75 ns ? upper turn-on propagation delay (hi rising to ho rising) t hplh ? 35 75 ns ? output rise/fall time t r/f ? 20 ? ns c l = 1000 pf output rise/fall time (3v to 9v) t r/f ? 0.8 ? sc l = 0.1 f minimum input pulse width that changes the output t pw ?50 ?ns note 4 switching specifications pwm mode (mic4607-2) or li/hi mode (mic4607-1) with overlapping li/hi inputs delay from pwm going high / li low , to lo going low t looff ?35 75 ns ? lo output voltage threshold for lo fet to be considered off v looff ? 1.9 ? v ? delay from lo off to ho going high t hoon ?35 75 ns ? delay from pwm or hi going low to ho going low t hooff ?35 75 ns ? dc characteristics ( note 1 , 2 ) (continued) electrical characteristics: unless otherwise indicated, v dd = v xhb = 12v; v en = 5v; v ss = v hs = 0v; no load on xlo or xho; t a = 25c; unless noted. bold values indicate ?40c< t j < +125c. parameters sym. min. typ. max. units conditions note 1: ?x? in front of a pin name refers to either a, b or c phase. (e.g. xhi can be either ahi, bhi or chi). 2: specification for packaged product only. 3: v il(max) = maximum positive voltage applied to the input which will be accepted by the device as a logic low. v ih(min) = minimum positive voltage applied to the input which will be accepted by the device as a logic high. 4: guaranteed by design. not production tested.
? 2016 microchip technology inc. ds20005610a-page 7 mic4607 switch node voltage threshold signaling ho is off v swth 1 2.2 4 v? delay between ho fet being considered off to lo turning on t loon ?35 75 ns ? forced xlo on if v swth is not detected t swto 100 250 500 ns ? temperature specifications electrical specifications: unless otherwise indicated, t a = +25c, v in = v en = 12v, v boost ? v sw = 3.3v, v out = 3.3v parameters sym. min. typ. max. units conditions temperature ranges operating junction temperature range t j ?40 ? +125 c ? operating ambient temperature range t a ?40 ? +125 c ? lead temperature ? ? 260 ? c soldering, 10s storage temperature range t s ?60 ? +150 c ? maximum junction temperature t j ? ? +125 c ? package thermal resistances thermal resistance, 4 mm 5 mm qfn-28l ? ja ? 43 ? c/w ? thermal resistance, 4 mm 5 mm qfn-28l ? jc ? 3.4 ? c/w ? tssop-28l ? ja ? 70 ? c/w ? tssop-28l ? jc ? 20 ? c/w ? dc characteristics ( note 1 , 2 ) (continued) electrical characteristics: unless otherwise indicated, v dd = v xhb = 12v; v en = 5v; v ss = v hs = 0v; no load on xlo or xho; t a = 25c; unless noted. bold values indicate ?40c< t j < +125c. parameters sym. min. typ. max. units conditions note 1: ?x? in front of a pin name refers to either a, b or c phase. (e.g. xhi can be either ahi, bhi or chi). 2: specification for packaged product only. 3: v il(max) = maximum positive voltage applied to the input which will be accepted by the device as a logic low. v ih(min) = minimum positive voltage applied to the input which will be accepted by the device as a logic high. 4: guaranteed by design. not production tested.
mic4607 ds20005610a-page 8 ? 2016 microchip technology inc. 2.0 typical performance curves figure 2-1: v dd quiescent current vs. v dd voltage. figure 2-2: v dd quiescent current vs. temperature. figure 2-3: v hb quiescent current (all channels) vs. v hb voltage. figure 2-4: v hb quiescent current (all channels) vs temperature. figure 2-5: v dd+hb shutdown current (floating switch node) vs. voltage. figure 2-6: v dd+hb shutdown current (floating switch node) vs. temperature. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. 280 310 340 370 400 430 460 490 5678910111213141516 i vdd quiescent current (a) v dd (v) -40c 25c 125c v xhs = gnd v en = 5v 280 300 320 340 360 380 400 420 440 460 480 500 -50 -25 0 25 50 75 100 125 i vdd quiescent current (a) temperature ( c) v dd = 16v v dd = 5.5v v dd = 12v v xhs = gnd v en = 5v 20 30 40 50 60 70 80 90 100 5 6 7 8 9 10 11 12 13 14 15 16 i v hb quiescent current (a) v hb (v) -40c 25c 125c v xhs = gnd v en = 5v 20 30 40 50 60 70 80 90 100 -50-25 0 255075100125 i vhb quiescent current (a) temperature ( c) v hb = 16v v hb = 5.5v v hb = 12v v xhs = gnd v en = 5v 0 1 2 3 4 5 6 7 8 5 6 7 8 9 10 11 12 13 14 15 16 i vdd+vhb shutdown current (a) v dd+hb (v) -40c 25c 125c xhi = xli = 0v v xhs = floating v en = 0v v dd = v hb 0 1 2 3 4 5 6 7 8 -50-25 0 255075100125 i vdd+vhb shutdown current (ua) temperature ( c) v dd = 16v v dd = 5.5v v dd = 12v xhi = xli = 0v v xhs = floating v en = 0v v dd = v hb
? 2016 microchip technology inc. ds20005610a-page 9 mic4607 figure 2-7: v dd+hb shutdown current (grounded switch node) vs. voltage. figure 2-8: v dd+hb shutdown current (grounded switch node) vs. temperature. figure 2-9: v dd+hb operating current vs. switching frequency. figure 2-10: v dd+hb operating current vs. switching frequency. figure 2-11: ho/lo sink on-resistance vs. v dd . figure 2-12: ho/lo sink on-resistance vs. temperature. 20 30 40 50 60 70 80 90 100 110 120 5 6 7 8 9 10 11 12 13 14 15 16 i vdd+vhb shutdown current (a) v dd+hb (v) -40c 25c 125c xhi = xl i= 0v v xhs = gnd v en = 0v v dd = v hb 20 30 40 50 60 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 i vdd+vhb shutdown current (a) temperature ( c) v dd = 16v v dd = 5.5v v dd = 12v xhi = xli = 0v v xhs = gnd v en = 0v v dd = v hb 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 0 102030405060708090100 i dd +v hb operating current (ma) frequency (khz) ?40oc 25oc 125oc v dd = 12v v xhs = 0v c load = 0nf 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2 0 102030405060708090100 i dd +v hb operating current (ma) frequency (khz) ?40oc 25oc 125oc v dd = 16v v xhs = 0v c load =0nf 5 10 15 20 25 5 6 7 8 9 10 11 12 13 14 15 16 r on source ( ?40oc 25oc 125oc i ho/lo = ?50ma v xhs = gnd v en = v hb = v dd 0 5 10 15 20 -50 -25 0 25 50 75 100 125 r on sink ( c) v dd = 16v v dd = 12v i ho/lo = 50ma v xhs = gnd v en = v hb = v dd v dd = 5.5v
mic4607 ds20005610a-page 10 ? 2016 microchip technology inc. figure 2-13: ho/lo source on-resistance vs. v dd . figure 2-14: ho/lo source on-resistance vs. temperature. figure 2-15: propagation delay (hi/li input) vs. v dd voltage. figure 2-16: propagation delay (hi/li input) vs. temperature. figure 2-17: output rise time vs. v dd voltage. figure 2-18: output fall time vs. v dd voltage. 5 10 15 20 25 5 6 7 8 9 10 11 12 13 14 15 16 r on source ( ?40oc 25oc 125oc i ho/lo = ?50ma v xhs = gnd v en = v hb = v dd 5 10 15 20 25 -50 -25 0 25 50 75 100 125 r on source ( c) v dd = 16v v dd = 12v i ho/lo = ?50ma v xhs = gnd v en = v hb = v dd v dd = 5.5v 20 30 40 50 60 70 5678910111213141516 delay (ns) v dd (v) t hplh t hphl t lplh t amb = 25c v xhs = 0v c l = 1nf t lphl 20 30 40 50 60 70 -50-25 0 255075100125 delay (ns) temperature (c) t hplh t hphl t lplh v dd = 12v v xhs = 0v c l =1nf t lphl 10 15 20 25 30 35 40 45 50 5678910111213141516 tr (ns) v dd (v) 25 c ?40 c 125 c v xhs = 0v c l = 1nf 5 10 15 20 25 30 35 40 45 5678910111213141516 tf (ns) v dd (v) 25 c ?40 c 125 c v xhs = 0v c l = 1nf
? 2016 microchip technology inc. ds20005610a-page 11 mic4607 figure 2-19: rise/fall time vs. temperature. figure 2-20: dead time vs. v dd voltage. figure 2-21: dead time vs. temperature. figure 2-22: v dd /v hb uvlo vs. temperature. figure 2-23: overcurrent threshold vs. v dd voltage. figure 2-24: overcurrent threshold vs. temperature. 5 10 15 20 25 30 35 40 45 50 55 -50 -25 0 25 50 75 100 125 tr/tf (ns) temperature ( c) rise time v dd = 5.5v v xhs = 0v c l =1nf rise time v dd = 12v fall time v dd = 12v fall time v dd = 5.5v 10 20 30 40 50 60 70 80 90 100 110 120 130 5678910111213141516 dead time (ns) v dd (v) ?40c v xhs = 0v c l =1nf t amb = 25c 25c 125c 10 20 30 40 50 60 70 80 90 100 110 120 130 -50 -25 0 25 50 75 100 125 dead time (ns) temperature (c) v dd = 12v v xhs = 0v c l =1nf v dd = 5.5v v dd = 12v v dd = 16v 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 -50-25 0 255075100125 uvlo threshold (v) temperature (c) v xhs = 0v v hb rising v hb falling v dd rising v dd falling
mic4607 ds20005610a-page 12 ? 2016 microchip technology inc. figure 2-25: overcurrent propagation delay vs. v dd voltage. figure 2-26: overcurrent propagation delay vs. temperature. figure 2-27: bootstrap diode reverse current. figure 2-28: bootstrap diode i-v characteristics. 50 60 70 80 90 100 110 120 5 6 7 8 9 10111213141516 propagation delay (ns) v dd (v) 25 c ?40 c 125 c v hs = 0v 50 60 70 80 90 100 110 120 -50 -25 0 25 50 75 100 125 propagation delay (ns) temperature ( c) v dd = 16v v dd = 12v v dd = 5.5v v xhs = 0v
? 2016 microchip technology inc. ds20005610a-page 13 mic4607 3.0 pin descriptions the descriptions of the pins are listed in table 3-1 . table 3-1: qfn pin function table pin number qfn pin name description mic4607-1 mic4607-2 1 bhi bpwm high-side input (-1) or pwm input (-2) for phase b. 2 ali nc low-side input (-1) or no connect (-2) for phase a. 3 ahi apwm high-side input (-1) or pwm input (-2) for phase a. 4enen active high enable input. high input enables all outputs and initiates normal operation. low input shuts down device into a low lq mode. 5flt/flt/ open drain . flt/ pin goes low when outputs are latched off due to an overcurrent event. must be pulled-up to an external voltage with a resistor . 6 bhb bhb phase b high-side bootstrap supply . an external bootstrap capacitor is required. connect the bootstrap capacitor across this pin and b hs . an on-board bootstrap diode is connected from v dd to b hb . 7 bho bho phase b high-side drive output . connect to the gate of the external high-side power mosfet. 8 bhs bhs phase b high-side driver return. connect to the bootstrap capacitor and to a resistor that connect to the source of the external mosfet. see the applications section for additional information on the resistor. 9 blo blo phase b low-side drive output . connect to the gate of the low-side power mosfet gate. 10 nc nc no connect . 11 ilim- ilim- differential current-limit input . connect to most negative end of the external current-sense resistor. 12 vss vss power ground for phase a and phase b . 13 ilim+ ilim+ differential current-limit input . connect to most positive end of the external current-sense resistor. 14 alo alo phase a low-side drive output . connect to the gate of the low-side power mosfet gate. 15 ahs ahs phase a high-side driver return . connect to the bootstrap capacitor and to a resistor that connect to the source of the external mosfet. see the applications section for additional information on the resistor. 16 aho aho phase a high side drive output . connect to the gate of the external high-side power mosfet. 17 ahb ahb phase a high-side bootstrap supply . an external bootstrap capacitor is required. connect the bootstrap capacitor across this pin and a hs . an on-board bootstrap diode is connected from v dd to a hb . 18 vdd vdd input supply for gate drivers and internal logic/control circuitry . decouple this pin to v ss with a minimum 2.2 f ceramic capacitor. 19 dly dly fault delay . connect an external capacitor from this pin to ground to increase the current-limit reset delay. leave open for minimum delay. do not externally drive this pin. 20 vss vss phase c power and control circuitry ground . 21 clo clo phase c low-side drive output . connect to the gate of the low-side power mosfet gate. 22 chs chs phase c high-side driver return. connect to the bootstrap capacitor and to a resistor that connect to the source of the external mosfet. see the applications section for additional information on the resistor.
mic4607 ds20005610a-page 14 ? 2016 microchip technology inc. 23 cho cho phase c high-side drive output. connect to the gate of the external high-side power mosfet. 24 chb chb phase c high-side bootstrap supply. an external bootstrap capacitor is required. connect the bootstrap capacitor across this pin and chs. an on-board bootstrap diode is connected from vdd to chb. 25 nc nc no connect. 26 cli nc low-side input (-1) or no connect (-2) for phase c. 27 chi cpwm high-side input (-1) or pwm input (-2) for phase c. 28 bli nc low-side input (-1) or no connect (-2) for phase b. ep epad epad exposed heatsink pad: connect to gnd for best thermal perfor- mance. table 3-2: tssop pin function table pin number tssop pin name description mic4607-1 mic4607-2 1 nc nc no connect. 2 cli nc low-side input (-1) or no connect (-2) for phase c. 3 chi cpwm high-side input (-1) or pwm input (-2) for phase c. 4 bli nc low-side input (-1) or no connect (-2) for phase b. 5 bhi bpwm high-side input (-1) or pwm input (-2) for phase b. 6 ali nc low-side input (-1) or no connect (-2) for phase a. 7 ahi apwm high-side input (-1) or pwm input (-2) for phase a. 8enen active high enable input. high input enables all outputs and initiates normal operation. low input shuts down device into a low lq mode. 9 flt/ flt/ open drain . flt/ pin goes low when outputs are latched off due to an overcurrent event. must be pulled-up to an external voltage with a resistor . 10 bhb bhb phase b high-side bootstrap supply . an external bootstrap capacitor is required. connect the bootstrap capacitor across this pin and b hs . an on-board bootstrap diode is connected from v dd to b hb . 11 bho bho phase b high-side drive output . connect to the gate of the external high-side power mosfet. 12 bhs bhs phase b high-side driver return. connect to the bootstrap capacitor and to a resistor that connect to the source of the external mosfet. see the applications section for additional information on the resistor. 13 blo blo phase b low-side drive output . connect to the gate of the low-side power mosfet gate. 14 ilim- ilim- differential current-limit input . connect to most negative end of the external current-sense resistor. 15 vss vss power ground for phase a and phase b . 16 ilim+ ilim+ differential current-limit input . connect to most positive end of the external current-sense resistor. 17 alo alo phase a low-side drive output . connect to the gate of the low-side power mosfet gate. table 3-1: qfn pin function table pin number qfn pin name description mic4607-1 mic4607-2
? 2016 microchip technology inc. ds20005610a-page 15 mic4607 18 ahs ahs phase a high-side driver return . connect to the bootstrap capacitor and to a resistor that connect to the source of the external mosfet. see the applications section for additional information on the resistor. 19 aho aho phase a high side drive output . connect to the gate of the external high-side power mosfet. 20 ahb ahb phase a high-side bootstrap supply . an external bootstrap capacitor is required. connect the bootstrap capacitor across this pin and a hs . an on-board bootstrap diode is connected from v dd to a hb . 21 vdd vdd input supply for gate drivers and internal logic/control circuitry . decouple this pin to v ss with a minimum 2.2 f ceramic capacitor. 22 dly dly fault delay . connect an external capacitor from this pin to ground to increase the current-limit reset delay. leave open for minimum delay. do not externally drive this pin. 23 vss vss phase c power and control circuitry ground . 24 clo clo phase c low-side drive output . connect to the gate of the low-side power mosfet gate. 25 chs chs phase c high-side driver return. connect to the bootstrap capacitor and to a resistor that connect to the source of the external mosfet. see the applications section for additional information on the resistor. 26 cho cho phase c high-side drive output . connect to the gate of the external high-side power mosfet. 27 chb chb phase c high-side bootstrap supply . an external bootstrap capacitor is required. connect the bootstrap capacitor across this pin and c hs . an on-board bootstrap diode is connected from v dd to c hb . 28 nc nc no connect . table 3-2: tssop pin function table pin number tssop pin name description mic4607-1 mic4607-2
mic4607 ds20005610a-page 16 ? 2016 microchip technology inc. 4.0 timing diagrams 4.1 non-overlapping li/hi input mode (mic4607-1) in non-overlapping li/hi input mode, enough delay is added between the xli and xhi inputs to allow xhs to be low before xli is pulled high and similarly xlo is low before xhi goes high. xho goes high with a high signal on xhi after a typical delay of 35 ns (t hplh ). xhi going low drives xho low also with typical delay of 35 ns (t hphl ). likewise, xli going high forces xlo high after typical delay of 35 ns (t lplh ) and xlo follows low transition of xli after typical delay of 35 ns (t lphl ). xho and xlo output rise and fall times (t r /t f ) are typi- cally 20 ns driving 1000 pf capacitive loads. figure 4-1: separate non-overlapping li/hi input mode (mic4607-1). note 1: all propagation delays are measured from the 50% voltage level and rise/fall times are measured 10% to 90%. 2: ?x? in front of a pin name refers to either a, b or c phase. (e.g. xhi can be either ahi, bhi or chi). t lplh t r t lphl t hplh t hphl t f t f t r xhs xho xlo xhi xli 0v
? 2016 microchip technology inc. ds20005610a-page 17 mic4607 4.2 overlapping li/hi input mode (mic4607-1) when xli/xhi input high signals overlap, xlo/xho out- put states are determined by the first output to be turned on. that is, if xli goes high (on), while xho is high, xho stays high until xhi goes low at which point, after a delay of t hooff and when xhs < 2.2v, xlo goes high with a delay of t loon . should xhs never trip the aforementioned internal comparator reference (2.2v), a falling xhi edge delayed by a typical 250 ns will set ?hs latch? allowing xlo to go high. if xhs falls very fast, xlo will be held low by a 35 ns delay gated by hi going low. conversely, xhi going high (on) when xlo is high has no effect on outputs until xli is pulled low (off) and xlo falls to < 1.9v. delay from xli going low to xlo falling is t looff and delay from xlo < 1.9v to xho being on is t hoon . figure 4-2: separate overlapping li/hi input mode (mic4607-1). t looff t hooff t loon t hoon xhs xho xlo xhi xli 2.2v (typ) 1.9v (typ) 0v
mic4607 ds20005610a-page 18 ? 2016 microchip technology inc. 4.3 pwm input mode (mic4607-2) a low going xpwm signal applied to the mic4607-2 causes xho to go low, typically 35ns (t hooff ) after the xpwm input goes low, at which point the switch node, xhs, falls (1 ? 2). when xhs reaches 2.2v (v swth ), the external high-side mosfet is deemed off and xlo goes high, typically within 35 ns (t loon ) (3-4). xhs falling below 2.2v sets a latch that can only be reset by xpwm going high. this design prevents ringing on xhs from causing an indeterminate xlo state. should xhs never trip the aforementioned internal comparator reference (2.2v), a falling xpwm edge delayed by 250 ns will set ?hs latch? allowing xlo to go high. a 35 ns delay gated by xpwm going low can determine the time to xlo going high for fast falling hs designs. xpwm going high forces xlo low in typically 35ns (t looff ) (5 ? 6). when xlo reaches 1.9v (v looff ), the low-side mos- fet is deemed off and xho is allowed to go high. the delay between these two points is typically 35 ns (t hoon ) (7 ? 8). xho and xlo output rise and fall times (t r /t f ) are typi- cally 20 ns driving 1000 pf capacitive loads. figure 4-3: pwm mode (mic4607-2). t looff (v looff ) t hoon xhs xho xlo xpwm t f t loon t r t hooff t r t f (v swth ) 4 3 2 5 6 1 7 0v
? 2016 microchip technology inc. ds20005610a-page 19 mic4607 4.4 overcurrent timing diagram the motor current is sensed in an external resistor that is connected between the low-side mosfet?s source pins and ground. if the sense resistor voltage exceeds the rising overcurrent threshold (typically 0.2v), all lo and ho outputs are latched off and the flt/ pin is pulled low. once the outputs are latched off, an internal current source (typically 0.44 a) begins to charge up the external c dly capacitor. the outputs remain latched off and all xli/xhi (or xpwm) input signals are ignored until the voltage on the c dly capacitor rises above the v dly+ threshold (typically 1.5v), which resets the latch on the first rising edge of any li input of the mic4607-1 (or falling edge on any pwm input for the mic4607-2). once this occurs, the c dly capacitor is discharged, the flt/ pin returns to a high impedance state and all out- puts will respond to their respective input signals. on startup, the current limit latch is reset during a rising v dd or a rising en pin voltage to assure normal opera- tion. figure 4-4: overcurrent timing diagram.
mic4607 ds20005610a-page 20 ? 2016 microchip technology inc. 5.0 functional description the mic4607 is a non-inverting, 85v three-phase mosfet driver designed to independently drive all six n-channel mosfets in a three-phase bridge. the mic4607 offers a wide 5.5v to 16v vdd operating supply range with either six independent ttl inputs (mic4607-1) or three pwm inputs, one for each phase (mic4607-2). refer to the functional diagram section. the drivers contain input buffers with hysteresis, four independent uvlo circuits (three high-side and one low-side), and six output drivers. the high-side output drivers utilize a high-speed level-shifting circuit that is referenced to its hs pin. each phase has an internal diode that is used by the bootstrap circuits to provide the drive voltages for each of the three high-side outputs. a programmable overcurrent protection circuit turns off all outputs during an overcurrent fault. 5.1 startup and uvlo the uvlo circuits force the driver?s outputs low until the supply voltage exceeds the uvlo threshold. the low-side uvlo circuit monitors the voltage between the vdd and vss pins. the high-side uvlo circuits monitor the voltage between the xhb and xhs pins. hysteresis in the uvlo circuits prevent system noise and finite circuit impedance from causing chatter during turn-on. 5.2 enable inputs there is one external enable pin that controls all three phases. a logic high on the enable pin (en) allows for startup of all phases and normal operation. conversely, when a logic low is applied on the enable pin, all phases turn-off and the device enters a low current shutdown mode. all outputs (xho and xlo) are pulled low when en is low. do not leave the en pin floating. 5.3 input stage all input pins (xli and xhi) are referenced to the v ss pin. the mic4607 has a ttl-compatible input range and can be used with input signals with amplitude less than the supply voltage. the threshold level is indepen- dent of the v dd supply voltage and there is no depen- dence between i vdd and the input signal amplitude. this feature makes the mic4607 an excellent level translator that will drive high level gate threshold mos- fets from a low-voltage pwm ic. 5.4 low-side driver the low-side driver is designed to drive a ground (v ss pin) referenced n-channel mosfet. low driver impedances allow the external mosfet to be turned on and off quickly. the rail-to-rail drive capability of the output ensures a low r dson from the external power device. refer to figure 5-1 . a high level applied to the xli pin causes v dd to be applied to the gate of the external mosfet. a low level on the xli pin grounds the gate of the external mosfet. figure 5-1: low-side driver block diagram. 5.5 high-side driver and bootstrap circuit figure 5-2 illustrates a block diagram of the high-side driver and bootstrap circuit. this driver is designed to drive a floating n-channel mosfet, whose source ter- minal is referenced to the hs pin. figure 5-2: high-side driver and bootstrap-circuit block diagram. a low-power, high-speed, level-shifting circuit isolates the low side (v ss pin) referenced circuitry from the high-side (xhs pin) referenced driver. power to the high-side driver and uvlo circuit is supplied by the bootstrap capacitor (c b ) while the voltage level of the xhs pin is shifted high. the bootstrap circuit consists of an internal diode and external capacitor, c b . in a typical application, such as the motor driver shown in figure 5-3 (only phase a illustrated), the ahs pin is at ground potential while the low-side mosfet is on. the internal diode charges capacitor c b to v dd -v f during this time (where v f is vss vdd lo external fet mic4607 switch node hs hb ho external fet vdd c b mic4607 level shift vin r hs switch node
? 2016 microchip technology inc. ds20005610a-page 21 mic4607 the forward voltage drop of the internal diode). after the low-side mosfet is turned off and the aho pin turns on, the voltage across capacitor c b is applied to the gate of the high-side external mosfet. as the high-side mosfet turns on, voltage on the ahs pin rises with the source of the high-side mosfet until it reaches v in . as the ahs and ahb pins rise, the inter- nal diode is reverse biased, preventing capacitor c b from discharging. during this time, the high-side mos- fet is kept on by the voltage across capacitor c b . figure 5-3: mic4607 motor driver example. 5.6 programmable gate drive the mic4607 offers programmable gate drive, meaning the mosfet gate drive (gate-to-source voltage) equals the v dd voltage. this feature offers designers flexibility in selecting the proper mosfets for a given application. different mosfets require different v gs characteristics for optimum r dson performance. typically, the higher the gate voltage (up to 16v), the lower the r dson achieved. for example, as shown in figure 5-4 , a ntmsf4899nf mosfet can be driven to the on state with a gate voltage of 5.5v but r dson is 5.2 m . if driven to 10v, r dson is 4.1 m ? a decrease of 20%. in low-current applications, the losses due to r dson are minimal, but in high-current motor drive applica- tions such as power tools, the difference in r dson can lower the efficiency, reducing run time. figure 5-4: mosfet r dson vs. v gs . 5.7 overcurrent protection circuitry the mic4607 provides overcurrent protection for the motor driver circuitry. it consists of: ? a comparator that senses the voltage across a current-sense resistor ? a latch and timer that keep all gate drivers off during a fault ? an open-drain pin that pulls low during the fault. if an overcurrent condition is detected, the flt/ pin is pulled low and the gate drive outputs are latched off for a time that is determined by the dly pin circuitry. after the delay circuitry times out, a high-going edge on any of the li pins (for the mic4607-1 version) or a low-going edge on any of the pwm pins (for the mic4607-2 version) is required to reset the latch, de-assert the flt/ pin and allow the gate drive outputs to switch. for additional information, refer to the timing diagrams section as well as the functional diagram section. 5.7.1 ilim the ilim+ and ilim- pins provide a kelvin-sensed cir- cuit that monitors the voltage across an external cur- rent sense resistor. this resistor is typically connected between the source pins of all three low-side mosfets and power ground. if the peak voltage across this resis- tor exceeds the vi lim+ threshold, it will cause all six out- puts to latch off. both pins should be shorted to v ss ground if the overcurrent features is not used. 5.7.2 dly a capacitor connected to the dly pin determines the amount of time the gate drive outputs are latched off before they can be restarted. during normal operation, the dly pin is held low by an internal mosfet. after an over-current condition is detected, the mosfet turns off and the external capacitor is charged up by an internal current source. the outputs remain latched off until the dly pin voltage reaches the v dly+ threshold (typically 1.5v). the delay time can be approximately calculated using equation 5-1 . equation 5-1: t dly c dly v dly - ? i dly ------------------------------------ - =
mic4607 ds20005610a-page 22 ? 2016 microchip technology inc. 5.7.3 flt/ this open-drain output is pulled low while the gate drive outputs are latched off after an over-current condition. it will de-assert once the dly pin has reached the v dly+ threshold and a rising edge occurs on any li pin (for the mic4607-1) or a falling edge on any pwm pin (mic4607-2). during normal operation, the internal pull-down mos- fet is of the pin is high impedance. a pull-up resistor must be connected to this pin.
? 2016 microchip technology inc. ds20005610a-page 23 mic4607 6.0 application information 6.1 adaptive dead time for each phase, it is important that both mosfets of the same phase branch are not conducting at the same time or v in will be shorted to ground and current will ?shoot through? the mosfets. excessive shoot-through causes higher power dissipation in the mosfets, voltage spikes and ringing. the high switch- ing current and voltage ringing generate conducted and radiated emi. minimizing shoot-through can be done passively, actively or through a combination of both. passive shoot-through protection can be achieved by imple- menting delays between the high and low gate drivers to prevent both mosfets from being on at the same time. these delays can be adjusted for different appli- cations. although simple, the disadvantage of this approach is that it requires long delays to account for process and temperature variations in the mosfet and mosfet driver. adaptive dead time monitors voltages on the gate drive outputs and switch node to determine when to switch the mosfets on and off. this active approach adjusts the delays to account for some of the varia- tions, but it too has its disadvantages. high currents and fast switching voltages in the gate drive and return paths can cause parasitic ringing to turn the mosfets back on even while the gate driver output is low. another disadvantage is that the driver cannot monitor the gate voltage inside the mosfet. figure 6-1 shows an equivalent circuit of the high-side gate drive. figure 6-1: mic4607 driving an external mosfet. the internal gate resistance (r g_fet ) and any external damping resistor (r g ) and hs pin resistor (r hs ), iso- late the mosfet?s gate from the driver output. there is a delay between when the driver output goes low and the mosfet turns off. this turn-off delay is usually specified in the mosfet data sheet. this delay increases when an external damping resistor is used. the mic4607 uses a combination of active sensing and passive delay to ensure that both mosfets are not on at the same time. figure 6-2 illustrates how the adaptive dead-time circuitry works. figure 6-2: adaptive dead-time logic diagram. for the mic4607-2, a high level on the xpwm pin causes hi to go low and li to go high. this causes the xlo pin to go low. the mic4607 monitors the xlo pin voltage and prevents the xho pin from turning on until the voltage on the xlo pin reaches the v looff thresh- old. after a short delay, the mic4607 drives the xho pin high. monitoring the xlo voltage eliminates any exces- sive delay due to the mosfet driver?s turn-off time and the short delay accounts for the mosfet turn-off delay as well as letting the xlo pin voltage settle out. if an external resistor is used between the xlo output and the mosfet gate, it must be made small enough to prevent excessive voltage drop across the resistor during turn-off. figure 6-3 illustrates using a diode (d ls ) and resistor (r ls2 ) in parallel with the gate resis- tor to prevent a large voltage drop between the xlo pin and mosfet gate voltages during turn-off. figure 6-3: low-side drive gate resistor configuration. a low on the xpwm pin causes hi to go high and lo to go low. this causes the xho pin to go low after a short delay (t hooff ). before the xlo pin can go high, the voltage on the switching node (xhs pin) must have dropped to 2.2v. monitoring the switch voltage instead of the xho pin voltage eliminates timing variations and excessive delays due to the high side mosfet
mic4607 ds20005610a-page 24 ? 2016 microchip technology inc. turn-off. the xlo driver turns on after a short delay (t loon ). once the xlo driver is turned on, it is latched on until the xpwm signal goes high. this prevents any ringing or oscillations on the switch node or xhs pin from turning off the xlo driver. if the xpwm pin goes low and the voltage on the xhs pin does not cross the v swth threshold, the xlo pin will be forced high after a short delay (t swto ), ensuring proper operation. the internal logic circuits also ensure a ?first on? priority at the inputs. if the xho output is high, the xli pin is inhibited. a high signal or noise glitch on the xli pin has no effect on the xho or xlo outputs until the xhi pin goes low. similarly, xlo being high holds xho low until xli and xlo are low. fast propagation delay between the input and output drive waveform is desirable. it improves overcurrent protection by decreasing the response time between the control signal and the mosfet gate drive. minimiz- ing propagation delay also minimizes phase shift errors in power supplies with wide bandwidth control loops. care must be taken to ensure that the input signal pulse width is greater than the minimum specified pulse width. an input signal that is less than the minimum pulse width can result in no output pulse or an output pulse whose width is significantly less than the input. the maximum duty cycle (ratio of high-side on-time to switching period) is determined by the time required for the c b capacitor to charge during the off-time. ade- quate time must be allowed for the c b capacitor to charge up before the high-side driver is turned back on. although the adaptive dead-time circuit in the mic4607 prevents the driver from turning both mosfets on at the same time, other factors outside of the anti-shoot-through circuit?s control can cause shoot-through. other factors include ringing on the gate drive node and capacitive coupling of the switching node voltage on the gate of the low-side mosfet. the scope photo in figure 6-4 shows the dead time (<20 ns) between the high- and low-side mosfet transitions as the low-side driver switches off while the high-side driver transitions from off to on. figure 6-4: adaptive dead-time lo (low) to ho (high). table 6-1 contains truth tables for the mic4607-1 (inde- pendent ttl inputs) and table 6-2 is for the mic4607-2 (pwm inputs) that details the ?first on? pri- ority as well as the failsafe delay (t swto ). 6.2 hs node clamp a resistor/diode clamp between the switching node and the hs pin is necessary to clamp large negative glitches or pulses on the hs pin. figure 6-5 shows the phase a section high-side and low-side mosfets connected to one phase of the three phase motor. there is a brief period of time (dead time) between switching to prevent both mosfets from being on at the same time. when the high-side mosfet is conducting during the on-time state, cur- rent flows into the motor. after the high-side mosfet turns off, but before the low-side mosfet turns on, current from the motor flows through the body diode in parallel with the low-side mosfet. depending upon the turn-on time of the body diode, the motor current, and circuit parasitics, the initial negative voltage on the switch node can be several volts or more. the forward voltage drop of the body diode can be several volts, depending on the body diode characteristics and motor current. even though the hs pin is rated for negative voltage, it is good practice to clamp the negative voltage on the hs pin with a resistor and possibly a diode to prevent excessive negative voltage from damaging the driver. depending upon the application and amount of nega- tive voltage on the switch node, a 3 resistor is recom- table 6-1: mic4607-1 truth table xli xhi xlo xho comments 0 0 0 0 both outputs off. 01 0 1 xho will not go high until xlo falls below 1.9v. 10 1 0 xlo will be delayed an extra 250 ns if xhs never falls below 2.2v. 11 x x first on stays on until input of same goes low. table 6-2: mic4607-2 truth table xpwm xlo xho comments 010 xlo will be delayed an extra 250 ns if xhs never falls below 2.2v. 101 xho will not go high until xlo falls below 1.9v.
? 2016 microchip technology inc. ds20005610a-page 25 mic4607 mended. if the hs pin voltage exceeds 0.7v, a diode between the xhs pin and ground is recommended. the diode reverse voltage rating must be greater than the high-voltage input supply (v in ). larger values of resis- tance can be used if necessary. adding a series resistor in the switch node limits the peak high-side driver current during turn-off, which affects the switching speed of the high-side driver. the resistor in series with the ho pin may be reduced to help compensate for the extra hs pin resistance. figure 6-5: negative hs pin voltage. 6.3 power dissipation considerations power dissipation in the driver can be separated into three areas: ? internal diode dissipation in the bootstrap circuit ? internal driver dissipation ? quiescent current dissipation used to supply the internal logic and control functions. 6.4 bootstrap circuit power dissipation power dissipation of the internal bootstrap diode pri- marily comes from the average charging current of the bootstrap capacitor (c b ) multiplied by the forward volt- age drop of the diode. secondary sources of diode power dissipation are the reverse leakage current and reverse recovery effects of the diode. the average current drawn by repeated charging of the high-side mosfet is calculated by equation 6-1 . equation 6-1: the average power dissipated by the forward voltage drop of the diode equals: equation 6-2: there are three phases in the mic4607. the power dis- sipation for each of the bootstrap diodes must be calcu- lated and summed to obtain the total bootstrap diode power dissipation for the package. the value of v f should be taken at the peak current through the diode; however, this current is difficult to calculate because of differences in source imped- ances. the peak current can either be measured or the value of v f at the average current can be used, which will yield a good approximation of diode power dissipa- tion. the reverse leakage current of the internal bootstrap diode is typically 3 a at a reverse voltage of 85v at 125c. power dissipation due to reverse leakage is typ- ically much less than 1 mw and can be ignored. an optional external bootstrap diode may be used instead of the internal diode ( figure 6-6 ). an external diode may be useful if high gate charge mosfets are being driven and the power dissipation of the internal diode is contributing to excessive die temperatures. the voltage drop of the external diode must be less than the internal diode for this option to work. the reverse voltage across the diode will be equal to the input voltage minus the v dd supply voltage. the above equations can be used to calculate power dissipation in the external diode; however, if the external diode has significant reverse leakage current, the power dissi- pated in that diode due to reverse leakage can be cal- culated with the formula in equation 6-3 : equation 6-3: the on-time is the time the high-side switch is conduct- ing. in most topologies, the diode is reverse biased during the switching cycle off-time. ahs ahb aho vdd c b alo level shift ahi ali vss v in c vdd mic4607 m r g r g r hs d clamp d bst v neg 3 phases b&c phase a i fave ?? q gate f s ? = where: q gate total gate charge at v hb ? v hs . f s gate drive switching frequency. pdiode fwd i fave ?? v f ? = where: v f diode forward voltage drop. pdiode rev i r v rev 1 d ? ?? ? ? = where: i r reverse current flow at v rev and t j . v rev diode reverse voltage. d duty cycle = t on f s .
mic4607 ds20005610a-page 26 ? 2016 microchip technology inc. figure 6-6: optional external bootstrap diode. 6.5 gate driver power dissipation power dissipation in the output driver stage is mainly caused by charging and discharging the gate to source and gate to drain capacitance of the external mosfet. figure 6-7 shows a simplified equivalent circuit of the mic4607 driving an external high-side mosfet. figure 6-7: mic4607 driving an external high-side mosfet. 6.5.1 dissipation during the external mosfet turn-on energy from capacitor c b is used to charge up the input capacitance of the mosfet (c gd and c gs ). the energy delivered to the mosfet is dissipated in the three resistive components, r on , r g and r g_fet . r on is the on resistance of the upper driver mosfet in the mic4607. r g is the series resistor (if any) between the driver and the mosfet. r g_fet is the gate resistance of the mosfet and is typically listed in the power mosfet?s specifications. the esr of capacitor c b and the resistance of the connecting etch can be ignored since they are much less than r on and r g_fet . the effective capacitances of c gd and c gs are difficult to calculate because they vary non-linearly with i d , v gs , and v ds . fortunately, most power mosfet spec- ifications include a typical graph of total gate charge versus v gs . figure 6-8 shows a typical gate charge curve for an arbitrary power mosfet. this chart shows that for a gate voltage of 10v, the mosfet requires about 23.5 nc of charge. the energy dissi- pated by the resistive components of the gate drive cir- cuit during turn-on is calculated as: equation 6-4: but equation 6-5: so, equation 6-6: figure 6-8: typical gate charge vs. v gs . e 1 2 -- - c iss ? v gs 2 ? = where: c iss total gate capacitance of the mosfet. qcv ? = e 1 2 -- - q g ? v gs ? =
? 2016 microchip technology inc. ds20005610a-page 27 mic4607 the same energy is dissipated by r off , r g , and r g_fet when the driver ic turns the mosfet off. assuming r on is approximately equal to r off , the total energy and power dissipated by the resistive drive ele- ments is: equation 6-7: and equation 6-8: 6.6 supply current power dissipation power is dissipated in the input and control sections of the mic4607, even if there is no external load. current is still drawn from the v dd and hb pins for the internal circuitry, the level shifting circuitry, and shoot-through current in the output drivers. the v dd and v hb currents are proportional to operating frequency and the v dd and v hb voltages. the typical performance curves show how supply current varies with switching fre- quency and supply voltage. the power dissipated by the mic4607 due to supply current is: equation 6-9: values for i dd and i hb are found in the ec table and the typical characteristics graphs. 6.7 total power dissipation and thermal considerations total power dissipation in the mic4607 is equal to the power dissipation caused by driving the external mos- fets, the supply currents and the internal bootstrap diodes. equation 6-10: where: e driver = energy dissipated per switching cycle. p driver = power dissipated per switching cycle. q g = total gate charge at v gs . v gs = gate-to-source voltage on the mosfet. f s = switching frequency of the gate drive circuit. the power dissipated in the driver equals the ratio of r on and r off to the external resistive losses in r g and r g_fet . letting r on = r off , the power dissipated in the driver due to driving the external mosfet is: equation 6-11: there are six mosfets driven by the mic4607. the power dissipation for each of the drivers must be calcu- lated and summed to obtain the total driver diode power dissipation for the package. in some cases, the high-side fet of one phase may be pulsed at a frequency, f s , while the low-side fet of the other phase is kept continuously on. since the mos- fet gate is capacitive, there is no driver power if the fet is not switched. the operation of all driver outputs must be considered to accurately calculate power dis- sipation. the die temperature can be calculated after the total power dissipation is known. equation 6-12: where: t a = maximum ambient temperature. t j = junction temperature (c). p disstotal = total power dissipation of the mic4607. ja = thermal resistance from junction to ambient air. 6.8 other timing considerations make sure the input signal pulse width is greater than the minimum specified pulse width. an input signal that is less than the minimum pulse width may result in no output pulse or an output pulse whose width is signifi- cantly less than the input. the maximum duty cycle (ratio of high-side on-time to switching period) is controlled by the minimum pulse width of the low side and by the time required for the c b capacitor to charge during the off-time. adequate time must be allowed for the c b capacitor to charge up before the high-side driver is turned on. 6.9 decoupling and bootstrap capacitor selection decoupling capacitors are required for both the low-side (v dd ) and high-side (xhb) supply pins. these capacitors supply the charge necessary to drive the external mosfets and also minimize the voltage rip- ple on these pins. the capacitor from xhb to xhs has e driver q g v gs ? = p driver q g v gs ? f s ? = pdiss supply v dd i dd v hb + ? i hb ? = pdiss total pdiss supply pdiss drive p diode ++ = pdiss driver p driver r on r on r g r g _fet ++ ------------------------------------------------- ? = t j t a pdiss total ? ja ? + =
mic4607 ds20005610a-page 28 ? 2016 microchip technology inc. two functions: it provides decoupling for the high-side circuitry and also provides current to the high-side cir- cuit while the high-side external mosfet is on. ceramic capacitors are recommended because of their low impedance and small size. z5u type ceramic capacitor dielectrics are not recommended because of the large change in capacitance over temperature and voltage. a minimum value of 0.1 f is required for c b (xhb to xhs capacitors) and 1 f for the v dd capacitor, regardless of the mosfets being driven. larger mos- fets may require larger capacitance values for proper operation. the voltage rating of the capacitors depends on the supply voltage, ambient temperature and the voltage derating used for reliability. 25v rated x5r or x7r ceramic capacitors are recommended for most applications. the minimum capacitance value should be increased if low voltage capacitors are used because even good quality dielectric capacitors, such as x5r, will lose 40% to 70% of their capacitance value at the rated voltage. placement of the decoupling capacitors is critical. the bypass capacitor for v dd should be placed as close as possible between the v dd and v ss pins. the bypass capacitor (c b ) for the xhb supply pin must be located as close as possible between the xhb and xhs pins. the etch connections must be short, wide, and direct. the use of a ground plane to minimize connection impedance is recommended. refer to the ? grounding, component placement and circuit layout ? sub-section for more information. the voltage on the bootstrap capacitor drops each time it delivers charge to turn on the mosfet. the voltage drop depends on the gate charge required by the mos- fet. most mosfet specifications specify gate charge versus v gs voltage. based on this information and a recommended v hb of less than 0.1v, the minimum value of bootstrap capacitance is calculated as: equation 6-13: where: q gate = total gate charge at v hb . v hb = voltage drop at the hb pin. if the high-side mosfet is not switched but held in an on state, the voltage in the bootstrap capacitor will drop due to leakage current that flows from the hb pin to ground. this current is specified in the electrical char- acteristics table. in this case, the value of c b is calcu- lated as: equation 6-14: where: i hbs = maximum xhb pin leakage current. t on = maximum high-side fet on-time. the larger value of c b from equation 6-13 or equation 6-14 should be used. 6.10 grounding, component placement and circuit layout nanosecond switching speeds and ampere peak cur- rents in and around the mic4607 driver require proper placement and trace routing of all components. improper placement may cause degraded noise immu- nity, false switching, excessive ringing, or circuit latch-up. figure 6-9 shows the critical current paths of the high- and low-side driver when their outputs go high and turn on the external mosfets. it also helps demonstrate the need for a low impedance ground plane. charge needed to turn-on the mosfet gates comes from the decoupling capacitors c vdd and c b . current in the low-side gate driver flows from c vdd through the inter- nal driver, into the mosfet gate, and out the source. the return connection back to the decoupling capacitor is made through the ground plane. any inductance or resistance in the ground return path causes a voltage spike or ringing to appear on the source of the mos- fet. this voltage works against the gate drive voltage and can either slow down or turn off the mosfet during the period when it should be turned on. current in the high-side driver is sourced from capaci- tor c b and flows into the xhb pin and out the xho pin, into the gate of the high side mosfet. the return path for the current is from the source of the mosfet and back to capacitor c b . the high-side circuit return path usually does not have a low-impedance ground plane so the etch connections in this critical path should be short and wide to minimize parasitic inductance. as with the low-side circuit, impedance between the mos- fet source and the decoupling capacitor causes neg- ative voltage feedback that fights the turn-on of the mosfet. it is important to note that capacitor c b must be placed close to the xhb and xhs pins. this capacitor not only provides all the energy for turn-on but it must also keep xhb pin noise and ripple low for proper operation of the high-side drive circuitry. c b q gate ? v hb ---------------- - ? c b i hbs t on ? ? v hb --------------------------- - ?
? 2016 microchip technology inc. ds20005610a-page 29 mic4607 figure 6-9: turn-on current paths. figure 6-10 shows the critical current paths when the driver outputs go low and turn off the external mos- fets. short, low-impedance connections are important during turn-off for the same reasons given in the turn-on explanation. current flowing through the inter- nal diode replenishes charge in the bootstrap capacitor, c b . figure 6-10: turn-off current paths.
mic4607 ds20005610a-page 30 ? 2016 microchip technology inc. 7.0 motor applications figure 7-1 illustrates an automotive motor application. the 12v battery input voltage can see peaks as high as 60v during a load dump event. the 85v-rated mic4607 drives six mosfets that provide power to the bldc motor. a current-sense resistor senses the peak motor cur- rent. the voltage across this resistor is monitored by the oc circuit in the mic4607, which provides overcur- rent protection for the application. the 120v rating of the mic5281 series of ldos provide input surge volt- age protection, while regulating the battery voltage down to 3.3v and 10v ? 12v for the microcontroller and gate driver respectively. this circuit can also be used for power tool applications, where the battery voltage carries high-voltage peaks and surges. figure 7-2 is a block diagram for a 24v motor drive application. the regulated 24v bus allows the use of lower input voltage ldos, such as the mic5239-3.3 and mic5234. this circuit configuration can be used in industrial applications. figure 7-3 illustrates an off-line motor application. add- ing an off-line power supply to the front end allow the mic4607 to be used in applications such as blenders and other small white goods as well as ceiling fan appli- cations. the circuit consists of an mic38c44 based ac/dc power supply, that is used to generate 24 vdc to power a bldc motor. the mic4607 drives the six mosfets that provide power to the motor. the mic4607 can also be used in low and mid-voltage inverter applications. figure 7-4 shows how power generated by a spinning (or breaking) motor can be used to generate dc power to a load or provide power for battery-charging applications. figure 7-1: automotive or power tool application.
? 2016 microchip technology inc. ds20005610a-page 31 mic4607 figure 7-2: industrial motor driver. figure 7-3: blender motor drive application diagram.
mic4607 ds20005610a-page 32 ? 2016 microchip technology inc. figure 7-4: three-phase synchronous rectification.
? 2016 microchip technology inc. ds20005610a-page 33 mic4607 8.0 packaging information 8.1 package marking information xxxx-x yyww xxxx -xxxx yyww 4607-1 1612 4607 -2yts 1612 24-lead vqfn* example 28-lead tssop* example legend: xx...x product code or customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. , , pin one index is identified by a dot, delta up, or delta down (triangle mark). note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. package may or may not include the corporate logo. underbar (_) symbol may not be to scale. 3 e 3 e
mic4607 ds20005610a-page 34 ? 2016 microchip technology inc. 28-lead qfn 4 mm x 5 mm package outline and recommended land pattern 28-lead tssop 5.0 mm x 4.4 mm package outline and recommended land pattern note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2016 microchip technology inc. ds20005610a-page 35 mic4607
mic4607 ds20005610a-page 36 ? 2016 microchip technology inc.
? 2016 microchip technology inc. ds20005610a-page 37 mic4607 appendix a: revision history revision a (august 2016) ? converted micrel document dsc2875 to micro- chip data sheet template ds20005610a. ? minor text changes throughout.
mic4607 ds20005610a-page 38 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005610a-page 39 mic4607 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . examples: a) MIC4607-1YML-T5: 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent pro- tection, dual inputs, ?40c to +125c tem- perature range, rohs compliant, 28-pin vqfn, 500/reel. b) mic4607-1yml-tr: 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent pro- tection, dual inputs, ? 40c to +125c temp. range, rohs compli- ant, 28-pin vqfn, 5000/reel. c) mic4607-1yts: 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent pro- tection, dual inputs, ? 40c to +125c temp. range, rohs compli- ant, 28-pin tssop, 50/ tube d) mic4607-1yts-t5: 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent pro- tection, dual inputs, ? 40c to +125c temp. range, rohs compli- ant, 28-pin tssop, 500/reel e) mic4607-1yts-tr: 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent pro- tection, dual inputs, ? 40c to +125c temp. range, rohs compli- ant, 28-pin tssop, 2500/reel. f) mic4607-2yml-t5: 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent pro- tection, single pwm input, ?40c to +125c temp. range, rohs compliant, 28-pin tssop, 500/reel. g) mic4607-2yml-tr: 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent pro- tection, single pwm input, ?40c to +125c temp. range, rohs compliant, 28-pin tssop, 2500/reel. h) mic4607-2yts: 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent pro- tection, dual inputs, ? 40c to +125c temp. range, rohs compli- ant, 28-pin tssop, 50/ p art no. x xx package junction temperature device device: mic4607: 85v, three-phase mosfet driver with adaptive dead-time, anti-shoot-through and overcurrent protection input option: 1 = dual inputs 2 = single pwm input temperature range: y = -40 ? c to +125 ? c (rohs compliant) package: ml = 28-lead 4x5 qfn ts = 28-lead 5.0x4.4 tssop media type: t5 = 500/reel tr = 5000/reel vqfn (ml) package = 2500/reel tssop (ts) package blank= 50/tube tssop (ts) package x input option range xx media ? type
mic4607 ds20005610a-page 40 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds00005610a-page 41 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, includ ing but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-0899-4 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification contained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
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